Lattice Launches New 3.3-Volt ispMACH 4000V CPLDs

Based Upon 3rd Generation 2.5ns SuperFAST(TM) Architecture; Also Completes Production Release of 2.5- and 1.8-volt ispMACH 4000B/C Families

HILLSBORO, Ore.--(BUSINESS WIRE)--May 13, 2002-- Lattice Semiconductor Corporation (Nasdaq:LSCC - News) today announced the immediate availability of a 3.3-volt series of ispMACH(TM) 4000 SuperFAST ISP(TM) CPLDs designated the ispMACH 4000V family.

In addition to releasing all densities of the ispMACH 4000V family, Lattice also released the final members of its industry-leading 2.5-volt and 1.8-volt ispMACH 4000B and ispMACH 4000C families. Lattice is now in volume production with 32-, 64-, 128-, 256-, 384- and 512-macrocell versions of all three families. The ispMACH 4000 devices couple industry-leading performance of up to 380MHz and 2.5ns tPD (pin-to-pin logic delay) with the lowest dynamic power consumption available while supporting I/O standards between 3.3 and 1.8 volts.

In addition to providing the industry's first fully production released 1.8-volt in-system programmable CPLDs, Lattice now bridges multiple supply voltage generations by offering the same product architecture and leadership performance specifications with 1.8-, 2.5- and 3.3-volt supply voltage options. These three ispMACH 4000 families represent the continued expansion of Lattice's third generation of Big, Fast and Wide (BFW III) products, and are a generation ahead of the competitive CPLD offerings in the marketplace today.

"This single CPLD architecture, available in three core voltages, with mainstream logic densities, industry-leading performance and lowest active power, provides system designers with a one-stop solution for CPLD design," said Stan Kopec, Vice-President of Marketing. "This family extends Lattice's leadership position in CPLD solutions."

The ispMACH 4000 product line provides logic designers with a single architecture that covers a wide range of logic capacities, with 6 logic density options from 32 to 512 macrocells in a variety of advanced package and I/O options. I/O counts range from 30 to 208 across the family. The devices provide optimal logic implementation for many glue logic, state machine, decoder, bridging, power-up, and signal handshaking functions. These functions are critical for the implementation of many high performance computing, communications, and industrial applications.

SuperFAST Performance

At 32 macrocells, the ispMACH 4032 provides 2.5ns pin-to-pin delay (tPD), 2.2ns clock-to-output delay (tCO), 1.8ns set-up time (tS), and 380MHz operating frequencies (fMAX), 25% faster than available competitive devices. At 512 macrocells, the ispMACH 4512 provides 3.5ns tPD, 3.0ns tCO, 2.2ns tS, and 300MHz fMAX, 58% faster than available competitive devices. Lattice's SuperFAST devices outperform the competition across all logic density points.

Lowest Dynamic Power Consumption

Traditionally, low power consumption has been an important issue only for designers of equipment with limited available power, a small percentage of total PLD applications. However, designers of high performance computing and communications systems, which traditionally have had relatively unlimited power budgets, are increasingly interested in lowering power consumption to reduce operating cost and enhance system reliability. Lattice designed the ispMACH 4000 family to provide the best performance available, coupled with significantly lower power for these mainstream PLD applications. Digital design techniques, coupled with the use of low power non-volatile cells, allow static current to be reduced to as low as 1.3 milliamps. The use of a 1.8-volt core provides reduced dynamic power consumption for the family. As a result, the ispMACH 4256 device typically dissipates 78% less power at 100MHz than other commercially available 2.5-volt CPLD solutions.

Supports LVTTL and Multiple LVCMOS Standards

The ispMACH 4000 devices have two I/O banks, each with their own power supply voltage that can be set at the appropriate voltage to support LVTTL and LVCMOS 3.3, 2.5, and 1.8-volt outputs. Device input buffers have programmable thresholds that support the above standards independent of the I/O bank voltage. This approach, coupled with the availability of 3.3-, 2.5- and 1.8-volt devices, gives designers the flexibility needed in today's multi-voltage environments.

All ispMACH 4000 devices are also Boundary Scan Testable (IEEE 1149.1) and in-system programmable through an IEEE 1532-compliant JTAG boundary scan interface.

Design Tools

The ispMACH 4000 product line is supported by Lattice's new ispLEVER(TM) design tools. The ispLEVER tools, Lattice's platform for next-generation logic design, provide designers with rapid access to the performance of the ispMACH 4000 devices while maximizing resource utilization. This is achieved through timing driven placement & routing coupled with optimized synthesis support from vendors such as Exemplar and Synplicity. Additional third-party EDA tool support is provided through industry standard EDIF netlist import and export. The ispLEVER software is available in PC as well as UNIX workstation versions.

Price and Availability

All devices in the ispMACH 4000V/B/C families are available now. Packages offered include 44-Thin Quad Flat Pack (TQFP), 48-TQFP, 100-TQFP, 128-TQFP, 176-TQFP, and 256-ball fine pitch Ball Grid Array (fpBGA). For high-volume applications, pricing for the 1.8-Volt ispMACH 4032C is projected to be less than $1.00, while the ispMACH 4512C will be priced below $15.00.

About Lattice Semiconductor

Oregon-based Lattice Semiconductor Corporation designs, develops and markets the broadest range of high-performance ISP(TM) programmable logic devices (PLDs), Field Programmable Gate Arrays (FPGAs) and Field Programmable System Chip (FPSC) devices. Lattice offers total solutions for today's system designs by delivering the most innovative programmable silicon products that embody leading-edge system expertise.

Lattice products are sold worldwide through an extensive network of independent sales representatives and distributors, primarily to OEM customers in the fields of communications, computing, computer peripherals, instrumentation, industrial controls and military systems. Company headquarters are located at 5555 NE Moore Court, Hillsboro, Oregon 97124 USA; Telephone 503/268-8000, FAX 503/268-8037. For more information on Lattice Semiconductor Corporation, access our World Wide Web site at http://www.latticesemi.com.

Statements in this news release looking forward in time are made pursuant to the safe harbor provisions of the Private Securities Litigation Reform Act of 1995. Investors are cautioned that forward-looking statements involve risks and uncertainties including market acceptance and demand for our new products, our dependencies on our silicon wafer suppliers, the impact of competitive products and pricing, technological and product development risks and other risk factors detailed in the Company's Securities and Exchange Commission filings. Actual results may differ materially from forward-looking statements.

Lattice Semiconductor Corporation, L (& design), Lattice (& design), in-system programmable, ispLEVER, SuperFAST, ispMACH, ISP and specific product designations are either registered trademarks or trademarks of Lattice Semiconductor Corporation or its subsidiaries in the United States and/or other countries.

GENERAL NOTICE: Other product names used in this publication are for identification purposes only and may be trademarks of their respective holders.

     Lattice Semiconductor Corporation
     Sean Hildenbrand, 503/268-8680
     Sean.hildenbrand@latticesemi.com